SN74AHC373PWR

SN74AHC373PWR is TI’s octal D-type latch with 3-state outputs in the SN74AHC family. It provides eight D inputs (D0–D7) and eight outputs (Q0–Q7), plus latch enable (LE) and output enable (OE).
- How it works: When LE is high, the outputs follow the inputs (transparent). When LE goes low, the outputs latch and hold the last data. OE is active-low; when OE is high, all outputs are tri-stated.
- Electricals: CMOS device operating from about 2.0 to 5.5 V; CMOS-level input thresholds; high-speed with low power.
- Packaging: PWR suffix indicates TI package type (commonly 20-pin DIP/SOIC variants).
- Applications: data buffering and storage, bus interfacing, address/data multiplexing, and any time-muxed data path in microcontroller/processor systems.
- Tips: use a decoupling capacitor near VCC, tie OE low for normal operation, ensure valid D data before LE transitions, and respect input ranges.
In short: an 8-bit, controllable latch with tri-state outputs for efficient data buffering and bus interfacing.

Equivalents for SN74AHC373PWR (8-bit, 3-state latch) include:
- 74AHC373 by NXP/Nexperia
- 74HC373 (TI and others)
- 74HCT373 (TTL-compatible inputs)
- 74LVC373 (low-voltage CMOS)
- older 74ALS373 / SN74ALS373 (Schottky, 5V)
Note: ensure voltage ranges, speed, and OE/LE pinout match your design before swapping.

- Pin count: 20 pins.
- Function: An eight-bit (octal) D-type transparent latch with 3-state outputs. D0–D7 are data inputs, Q0–Q7 are outputs. LE (Latch Enable) controls when D is latched to Q; OE (Output Enable) controls tri-state output of Qn (outputs can be enabled or put in high-impedance). Includes Vcc and GND pins.

Manufacturer: Texas Instruments (TI).
What kind of company: TI is a multinational American semiconductor company that designs and manufactures analog and digital integrated circuits and other electronics components, with headquarters in Dallas, Texas.

SN74AHC373PWR is an 8-bit transparent latch with 3-state outputs (D inputs → Q outputs when LE is high; Q holds when LE is low; outputs tri-stated by G).
Common application areas:
- Latching address/data on multiplexed buses (e.g., microprocessor/memory interfaces)
- Data buffering and fan-out to peripheral devices
- Glue logic to bridge speed/mamily differences between CPUs/FPGAs and slower peripherals
- Bus interfacing and I/O expansion for digital systems
- General-purpose register/latch in digital designs
Operates from 2 V to 5.5 V, suitable for parallel 8-bit data paths.

PowerPAD package with an exposed pad, 20 pins (20‑pin small‑outline package in the TSSOP/HTSSOP family).