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SN74LVC1G97DRYR
+Lista de MateriaisIC CONFIG MULTI-FUNC GATE 6SON
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FabricanteTexas Instruments
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Peça do Fabricante #SN74LVC1G97DRYR
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Pacote UFDFN-6
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Especificações
| Atributo | Valor |
| Package / Case | Tape & Reel (TR),Cut Tape (CT),Bulk |
| Series | 74LVC |
| Part Status | Active |
| Logic Type | Configurable Multiple Function |
| Number of Circuits | 1 |
| Number of Inputs | 3 |
| Schmitt Trigger Input | No |
| Output Type | Single-Ended |
| Current - Output High Low | 32mA, 32mA |
| Voltage - Supply | 1.65V ~ 5.5V |
| Operating Temperature | -40°C ~ 125°C |
| Mounting Type | Surface Mount |
Visão Geral
Description
Equivalent
- 74LVC1G97 (Nexperia)
- 74LVC1G97 (NXP)
- 74LVC1G97 (ON Semiconductor)
Note: packaging, voltage range, and suffixes vary by supplier (PW, DW, DR, etc.). Use a cross-reference tool to confirm footprint and supply voltage for your design.
Features
- 1-bit, positive-edge-triggered D-type flip-flop
- Asynchronous clear (active-low)
- Q and Q̅ outputs
- Supply voltage 1.65 V to 3.6 V (LVC family)
- CMOS input thresholds; TTL-compatible inputs
- Low-power, high-speed operation
- Very small 6-pin package (DRYR: SC-70/SOT-23-6) with RoHS compliance
- ESD protection on pins (typical robust I/O protection)
Applications: simple memory elements, timing and sequencing circuits, and other small-form-factor digital logic needs.
Pinout
Function: SN74LVC1G97DRYR is a single-bit, edge-triggered D-type register/flip-flop with a tri-state output. It captures data on the rising edge of the clock input (CLK) and presents the stored value at Q, with an output-enable (OE) control to enable/disable the Q output.
Manufacturer
- What kind of company: An American multinational semiconductor company that designs and manufactures analog and embedded processing integrated circuits (one of the world’s largest semiconductor producers), headquartered in Dallas, Texas.
Application
- State machines and control logic
- Data storage and synchronization between blocks
- Clock division/toggle functions (divide-by-2)
- Simple counters and sequencing circuits
- Debouncing or pulse-shaping interfaces
- Interfacing MCUs/FPGA with external timing signals in 1.65–3.6 V systems